Field of the Invention
The invention relates to a semiconductor Non-Volatile Memory (NVM) device and methods of fabrication. In particular, the channel of the semiconductor NVM device is recessed in silicon substrate surfaces.
Description of the Related Art
Semiconductor Non-Volatile Memory (NVM), and particularly Electrically Erasable, Programmable Read-Only Memories (EEPROM), exhibits wide spread applicability in a range of electronic equipment from computers, to telecommunications hardware, to consumer appliances. In general, EEPROM serves a niche in the NVM space as a mechanism for storing firmware and data that can be kept even with power off and can be altered as needed. The flash EEPROM may be regarded as a specifically configured EEPROM that may be erased only on a global or sector-by-sector basis.
EEPROM flash is categorized into NOR-type flash and NAND-type flash according to its device cell array configuration. Usually, the cell sizes of NOR-type flash and NAND-type flash are 9˜10 F2 and 4˜5 F2, respectively, where F is the feature size for a process technology node. With the advanced process technology, the minimal process features have been scaled to around 20 nm nodes and below. Continuously scaling down semiconductor NVM cell device below 20 nm node poses significant challenges in cell device design and process technology. Those challenges include device short channel length, floating gate cell-to-cell interference, high aspect ratio for the gate formation process and the after-etched gate stack stability from collapsing.
To resolve the similar short channel length issue for scaling down DRAM (Dynamic Random Access Memory), recess gate transistor structures have been successfully applied to DRAM cells, such as U.S. Pat. Nos. 7,164,170, 7,378,312, and 8,268,690 (the disclosures of which are incorporated herein by reference in their entirety). For the cross-section view illustrated in FIG. 1, the recess channels 111a and 111b of paired access transistors 110a and 110b are formed along the bottom of recess surfaces in silicon substrate with N-type common source/drain regions 104c, 104a and 104b on or above the silicon substrate. The P-type impurity profiles in the P-type silicon substrate are channel region 102, well region 101, and substrate intrinsic region 100. The gate material is then deposited into the recess region on top of the grown oxides 105 on the silicon surface to form the transistor gate 106. The pairs of access transistors 110a and 110b in a memory array are isolated by the shallow trench isolations 103 in the silicon substrate. The channel lengths of the access transistors 110a and 110b thus increase for the recess channels 111a and 111b in comparison with the gate lengths of the conventional planar transistors processed with the same minimal feature node as shown in FIG. 1. The application of the recess channel for the access transistors in DRAM has greatly improved the charge retention time for the storage capacitors by reducing the “off-state” leakage currents of the access transistors, and can extend the DRAM process scalability down to the 20 nm nodes. On the other hand, the semiconductor non-volatile memory scaling issues such as channel length, floating-gate interference, and high aspect etch ratios can be resolved by applying the floating-gate recess channel transistor as well. First, like the access transistors 110a and 110b in advanced DRAM technology nodes, the floating-gate recess channel transistor gains its channel length by recessing the channel in the silicon substrate. Second, instead of exposing the floating-gates on the silicon surface, the floating-gate is embedded inside the ground potential silicon substrate and the cell-to-cell threshold voltage interference between floating-gates is also minimized. Third, by recessing the floating-gate accordingly with the recessed channel of the semiconductor NVM device in the silicon substrate, the high aspect gate etching ratio for the tunneling dielectrics/poly-silicon/coupling dielectrics/metal film stack is thus relieved. Meanwhile the holding strength of the tall slim-shape gate is also increased due to the gate film stack anchored inside the silicon substrate.